NVIDIA is putting its Vera CPU into the electronic design automation workflows used to create the company's next generations of CPUs and GPUs. The internal deployment turns Vera into part of NVIDIA's own chip-development toolchain, while joint optimisation work with Cadence and Synopsys is targeting verification and simulation applications that remain heavily dependent on CPU performance.

The company reported up to 1.5 times higher performance in early testing of selected production-class workloads using Cadence Jasper and Synopsys VCS. These results are potentially meaningful for engineering teams because verification can consume substantial time across a chip program, but they are limited claims rather than a comprehensive benchmark of the Vera platform.

Where the early performance gains appeared

Cadence Jasper is used for formal verification, where engineering teams mathematically analyse a design to find defects and establish that required properties hold. Synopsys VCS is a functional verification system used to simulate and validate complex digital designs before fabrication. NVIDIA says both applications recorded performance improvements of up to 1.5 times on selected workloads.

For the VCS test, NVIDIA states that the comparison used the same number of CPU cores. The announcement does not provide the full system configurations, workload sizes, compiler settings, power measurements or absolute completion times. It also does not say that every Jasper or VCS workload will achieve the maximum result. Buyers and engineering teams would need more complete data to compare Vera with alternative CPU platforms for their own EDA environments.

NVIDIA is working with Cadence and Synopsys on profiling, software optimisation and system-level tuning. That collaboration is intended to broaden performance improvements beyond the initial tests. No new commercial editions of Jasper or VCS were announced, and the post does not specify when optimised configurations will be generally available to customers.

Why EDA remains demanding for CPUs

Modern processor development involves repeated cycles of logic simulation, formal verification, regression testing and digital implementation. Engineers use these processes to identify corner cases and confirm behaviour before a design reaches manufacturing. A late defect can trigger costly rework, so shortening verification runs or increasing the number of tests completed within a development window can have an outsized effect on a program.

GPUs and AI already accelerate parts of chip design, but not every EDA task maps efficiently to parallel accelerators. Logic simulation and formal verification can rely on fast individual CPU cores, low memory latency and consistent throughput across large compute farms. NVIDIA is positioning Vera as the processor for those CPU-bound stages, alongside GPUs and AI acceleration used elsewhere in the workflow.

This distinction is important. The announcement does not claim that Vera replaces GPUs in chip design or that one architecture is optimal for every EDA task. Instead, NVIDIA describes a mixed approach in which each workload runs on the compute architecture best suited to it.

Vera's architecture for engineering workloads

Vera combines 88 custom NVIDIA Olympus CPU cores with an LPDDR5X memory subsystem and the second generation of NVIDIA Scalable Coherent Fabric. NVIDIA says the design targets strong per-core performance, memory bandwidth and predictable low latency.

Those characteristics are relevant to two different EDA patterns. A latency-sensitive verification job benefits when an individual run completes sooner. A large regression campaign benefits when the system can sustain many jobs and process more test cases in the same period. Improving both can let engineers explore more alternatives or find issues earlier, although actual gains will depend on the design, tool version and cluster configuration.

NVIDIA says it is deploying Vera throughout the EDA workflows used to build future processors. This creates a feedback loop: internal engineers exercise the CPU on demanding production work, and lessons from that use can inform software tuning and later processor designs. It also provides NVIDIA with a reference deployment for discussions with semiconductor and infrastructure customers.

What comes next

The company plans to continue its CPU roadmap with Rosa, a future processor using the NVIDIA Rigel core. The Vera deployment therefore represents both an operational change and an early step in a longer product cycle. NVIDIA did not provide a date for Rosa in this announcement.

For external users, several commercial questions remain unanswered. The post does not include Vera system pricing, a general availability schedule for EDA customers, supported server configurations or a detailed list of qualified tool versions. It also does not provide independent verification of the performance figures.

The announcement nevertheless shows a concrete use for NVIDIA's first custom data-centre CPU beyond hosting agentic AI workloads. By deploying Vera in its own chip-design process, NVIDIA is testing whether the processor's per-core performance and memory system can reduce bottlenecks in the workflows that produce future NVIDIA silicon. Broader significance will become clearer when complete benchmarks and customer deployment options are available.